1. Field of the Invention
The present invention relates generally to electronic devices, such as memory devices. More particularly, the present invention relates to a device and method for efficiently testing interconnections of electronic devices.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Microprocessor-controlled circuits are used in a wide variety of applications. Such applications include personal computers, control systems, telephone networks, and a host of other consumer products. A personal computer or control system includes various components, such as microprocessors, that handle different functions for the system. By combining these components, various consumer products and systems may be designed to meet specific needs. Microprocessors are essentially generic devices that perform specific functions under the control of software programs. These software programs are generally stored in one or more memory devices that are coupled to the microprocessor or other peripherals.
Semiconductor memory devices, such as dynamic random access memory (DRAM) devices, are widely used for storing data in systems such as computer systems. These memory devices are generally coupled to a substrate, such as a printed circuit board (PCB), by employing a surface mounting technique (SMT). Fine pitch surface mount (FPT), pin grid array (PGA), and ball grid array (BGA) are examples of leading surface mount technologies. As will be appreciated, BGA technology offers several advantages over FPT and PGA. Among the most often cited advantages of BGA are reduced co-planarity problems, since there are no leads; reduced placement problems; reduced paste printing problems; reduced handling damage; smaller size; better electrical and thermal performance; better package yield; better board assembly yield; higher interconnect density; multi-layer interconnect options; higher number of inputs and outputs for a given footprint; easier extension to multi-chip modules; and faster design-to-production cycle time.
A BGA semiconductor package generally includes a semiconductor chip mounted to a substrate. The semiconductor chip may be electrically coupled to the substrate by bond wires. The substrate contains conductive routing which allows the signals to pass from the semiconductor chip on the substrate, through the substrate, and to connection pads on a lower portion of the substrate. A plurality of solder balls are deposited and electrically coupled to the connection pads on the backside of the substrate to be used as input/output terminals for electrically connecting the substrate to a PCB or other external device. Once the BGA package is secured to a PCB or other device, however, the package itself obscures the connections between the package and the PCB or device, which increases the difficulty associated with identifying soldering faults, such as electrical shorts and opens, and generally verifying that the package is properly connected.
While various x-ray machines and special microscopes have been developed in an attempt to overcome some of these difficulties, it will be appreciated that these solutions are incomplete and expensive to implement. Additionally, boundary scans, such as the JTAG standard published by IEEE, allow some connections of a memory device to be tested. However, JTAG requires extra device interconnections, adds die size, is time consuming, and may impact loading to higher speed I/O. Further, JTAG does not support testing of certain connections, such as power and ground connections.
There is a need, therefore, for devices and methods that facilitate efficient testing of all interconnections between connection pads of two substrates, such as a substrate of an integrated circuit (I/C) device and a PCB. There is a further need for devices and methods that enable such testing without increasing the die size or affecting the operation of the I/C devices.